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Add initial support for the ROC-RK3588 AArch64 board.
It features a quad-core Cortex-A55 CPU based on the ARMv8.2 architecture.
This commit also enables SMP, allowing all four cores to run the synchronization sample.
In future, we will add support for the AArch32-mode zephyr on RK3588. Zephyr will run as an aarch32 guest vm on the aarch64 hypervisor.
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Add initial device tree support for the Rockchip RK3588 SoC.
The DTS describes:
- Four Cortex-A55 cores with PSCI enable-method
- GICv3 interrupt controller
- ARMv8 timer
- UART2 and UART3 (disabled by default)
Signed-off-by: Guowei Li <[email protected]>
Add initial support for the ROC-RK3588 AArch64 board.
It features a quad-core Cortex-A55 CPU based on the ARMv8.2 architecture.
This commit also enables SMP, allowing all four cores to run the
synchronization sample.
Signed-off-by: Guowei Li <[email protected]>
Sorry, I have fixed problems again and when I run ./scripts/ci/check_compliance.py -c upstream/main.., the output is this:
It seems that I don't have to fix these issues?
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Add initial support for the ROC-RK3588 AArch64 board.
It features a quad-core Cortex-A55 CPU based on the ARMv8.2 architecture.
This commit also enables SMP, allowing all four cores to run the synchronization sample.
In future, we will add support for the AArch32-mode zephyr on RK3588. Zephyr will run as an aarch32 guest vm on the aarch64 hypervisor.